Lead SoC Design Engineer

10+ years of experience in developing complex ASICs in advanced nodes.

Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB).

Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).

Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.

Experience designing with multiple power domains and UPF.

Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).

Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.

Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.

Partner with verification team:

Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.

Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.