asteralabs
Physical Design Engineer (Place & Route)
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At a Glance
- Location
- San Jose, California, United States
- Experience
- 3+ years
- Posted
- 2026-05-06T21:15:55-04:00
Key Requirements
Domain Knowledge
- Engineering
Requirements
Strong academic and technical background in electrical engineering.
3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Think and act fast with the customer in mind!
Knowledge of design for test (DFT).
Familiarity with ECO methodologies and tools.
Knowledge of LVS/DRC closures.