Sr. Staff Engineer - Timing Methodology

on our solutions to deliver AI to edge environments.

Our hardware and software innovations fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs without expensive process geometry scaling.

began in 2010 by addressing the power consumption challenges of battery-powered devices at the edge, where they

As of the beginning of 2025,

million units worldwide.

Our innovative and fast-moving teams of design, research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin

In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.

Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing      margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power.

Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of  Ips, namely, hard IP, Stdcell and Memory etc.

Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si.

Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA.

Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency.

Ambiq's

mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions.

Ambiq

is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub- and near-threshold technologies. With

the increasing