asteralabs

Senior Digital Design Engineer (AI Fabric)

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At a Glance

Location
San Jose, California, United States
Experience
3–8 years
Posted
2026-02-23T19:08:15-05:00

Key Requirements

Domain Knowledge

  • Automation
  • Embedded Systems
  • Engineering

Requirements

3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus

Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

Responsibilities

Own the RTL implementation of complex digital designs from micro-architecture through sign-off.

Collaborate with verification teams to review test plans and debug issues.

Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.

Scripting and automation for ASIC methodology improvement.

Accountable for quality and overall design success with the support of senior engineers.