asteralabs
Senior Principal Technologist – Memory
At a Glance
- Location
- San Jose, California, United States
- Compensation
- nt experience Salary range is $205,000 to $255,000 depending on experience, leve
- Posted
- 2026-05-18T14:23:06-04:00
Key Requirements
Domain Knowledge
- Engineering
Requirements
≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers
Deep experience with PCIe 5/6, and CXL including protocol level depth
Expertise in OS software integration including memory allocation/management
Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)
Deep expertise and understanding of memory components (DRAM, etc)
Strong understanding of datacenter system architecture and design challenges
Responsibilities
Are you passionate about pushing the boundaries of system, memory, software, and chip architecture?
Do you thrive when pitching cutting-edge technology solutions to customers and industry partners?
We are seeking a creative customer facing Technologist to help facilitate Astera’s development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design.
You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers’ bottlenecks in hyperscale data centers.